ARM system-on-chip architecture by Steve Furber

By Steve Furber

The way forward for the pc and communications industries is converging on cellular info home equipment - telephones, PDAs, laptops and different units. The ARM is on the middle of this development, top the way in which in system-on-chip (SoC) improvement and changing into the processor middle of selection for lots of embedded purposes. System-on-chip know-how is altering the way in which we use desktops, however it additionally units designers the very demanding challenge of having a fancy SoC layout correct first time. ARM System-on-Chip structure introduces the thoughts and methodologies hired in designing a system-on-chip dependent round a microprocessor center, and in designing the middle itself. broad illustrations, in keeping with the ARM, supply functional substance to the layout ideas set out within the booklet, reinforcing the reader's figuring out of the way and why SoCs and microprocessors are designed as they are.ARM System-on-Chip structure: · offers and discusses the main problems with system-on-chip layout, together with reminiscence hierarchy, caches, reminiscence administration, on-chip buses, on-chip debug and creation attempt · presents an summary of the ARM processor relations, allowing the reader to choose which ARM is better for the task in hand · describes the ARM and Thumb programming types, permitting the clothier to start to increase purposes · covers all of the most up-to-date ARM items and advancements, together with StrongARM, the ARM9 and ARM10 sequence of cores, and the ARM-based SoC parts on the middle of Ericsson's Bluetooth know-how, the Psion sequence five PDA and Samsung's SGH2400 GSM handset · contains info at the AMULET asynchronous ARM cores and the AMULET3H asynchronous SoC subsystemARM System-on-Chip structure is a necessary guide for system-on-chip designers utilizing ARM processor cores and engineers operating with the ARM. it might probably even be used as a path textual content for undergraduate and masters scholars of machine technology, computing device engineering and electric engineering.

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In the absence of a cache, poor code density leads to more main memory bandwidth being used for instruction fetching, resulting in a higher memory power consumption. When the processor incorporates an on-chip cache of a particular size, poor code density results in a smaller proportion of the working set being held in the cache at any time, increasing the cache miss rate, resulting in an even greater increase in the main memory bandwidth requirement and consequent power consumption. ARM code density and Thumb The ARM processor design is based on RISC principles, but for various reasons suffers less from poor code density than most other RISCs.

Minimize the power supply voltage, Vdd. The quadratic contribution of the supply voltage to the power dissipation makes this an obvious target. This is discussed further below. 2. Minimize the circuit activity, A. Techniques such as clock gating fall under this heading. Whenever a circuit function is not needed, activity should be eliminated. 3. Minimize the number of gates. Simple circuits use less power than complex ones, all other things being equal, since the sum is over a smaller number of gate contributions.

Reducing Vdd As the feature size on CMOS processes gets smaller, there is pressure to reduce the supply voltage. This is because the materials used to form the transistors cannot withstand an electric field of unlimited strength, and as transistors get smaller the field strength increases if the supply voltage is held constant. However, with increasing interest in design specifically for low power, it may be desirable for the supply voltage to be reduced faster than is necessary solely to prevent electrical breakdown.

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